1. Technical Field
The present invention relates to application specific integrated circuits (ASICs) and, more particularly, to testing thereof.
2. Description of Related Art
Most manufactured electronic PBAs are designed primarily using off-the-shelf ICs and the ASICs. Therefore, the current PBA test philosophy is based on board-level-test techniques. See Colin M. Maunder, Rodham E. Tullos, "The Test Access Port and Boundary-Scan Architecture". IEEE Computer Society Press, Los Alamitos, Calif. 1990. However, an increasing number of ASIC applications gives us the opportunity to utilize new methods in manufacturing test processes. One of these methods is a boundary-scan test method. See J. A. Waicukauski, E. Lindbloom, B. Rosen, V. Iyengrar, "Transition Fault Simulation by Parallel Pattern Single Fault Propagation", International Test Conference 1994 Proceedings, "TEST: The Next 25 Years" pp. 253-259, International Test Conference 205 Tennyson Ave, Suite C Altoona, Pa. 16602. Published in 1994.
The Boundary-Scan technique and technology defined by IEEE Std 1149.1a-1993 "IEEE Standard Test Access Port and Boundary-Scan Architecture", IEEE Std 1149.1a-1993, Institute of Electrical and Electronics Engineers, Inc. approved Jun. 17, 1993, published Oct. 21,1993, N.Y., USA describes the test logic implementation for integrated circuits (IC) to provide standardized test of ICs as they interact in an assembled product. The overall block Diagram of IEEE Std 1149.1a-1993 boundary-scan architecture at the component level is shown in FIG. 1.
The signals shown are standard inputs and outputs:
TCK (test clock)--the clock used to drive the TAP controller and boundary scan circuitry. PA1 TDI (test data in)--the input for a serialized instruction or test data. Data at TDI is clocked in on the rising edge of TCK. PA1 TDO (test data out)--the output for a serialized test data. Data is clocked out at TDO on the falling edge of TCK. PA1 TMS (test mode select)--this input provides a means to control the BSCAN TAP controller. The TMS state is sampled on the rising edge of TCK. PA1 TRST (test reset)--this optional input is an asynchronous reset of the TAP controller. PA1 (i) said provisioning/status interface for normal usage, and PA1 (ii) said BSCAN interface for testing usage, for storing said provisioning data and/or for retrieving said stored status data. PA1 1. PBA test cost and development time reduced, PA1 2. PBA resident ASIC functional tests can be easily performed, and PA1 3. Regression testing of Fault isolation for software verification can be easily performed. PA1 1/3 Capital cost (purchased commercial test equipment and controllers), PA1 1/3 Software development, and PA1 1/3 Design, build and documentations.
Internal data is captured and transmitted by setting up specific instructions with corresponding data registers to access and retrieve data. FIG. 2 is a diagram of the state machine employed by the BSCAN interface which allows instructions and data to be shifted into, and data to be shifted out of, the device under test.
The boundary scan architecture and state machine as shown in FIGS. 1 and 2 are imbedded in a BSCAN interface (BSCAN) as shown in an ASIC under test in FIG. 3 of the prior art. A standardized test interface to this boundary scan architecture includes a BSCAN control and an interface to a test set controller with a vector signal line (vector) referring to the test control language, a general-purpose interface bus (GPIB), a VME extension for an instrumentation bus (VXI) and a standard serial link (RS-232). The test set controller sends and receives data signals to and from the ASIC under test to verify proper functionality. The test set controller is designed specially for the ASIC to be tested via the pins under test line of FIG. 3. The design of such a test set controller is quite expensive.
The Standard permits "Private Instructions". Private Instructions allow the use of Test Access Port (TAP) and test logic to gain access to test features embedded in the design for design verification, production testing, or fault diagnosis (IEEE Std 1149.1a-1993, par. 7.3).
The RUNBIST Instruction permits all components to execute their self-test concurrently, providing rapid test of assembled boards (IEEE Std 1149.1a-1993, par. 7.9).
The Standard permits the use of the Built In Logic Block Observer (BILBO)--a shift register based structure used in some forms of self-testing circuit design. B. Koenemann, J. Mucha, G. Zweihoff, "Built-in Test for Complex Digital Integrated Circuits", IEEE J. Solid-State Circuits, Vol. SC-15, No. 3, pp. 315-318.
The Boundary-Scan Register may have parallel input and output cells. These inputs/outputs may also be connected to the internal logic (IEEE Std 1149.1a-1993, par. 10).
The Collateral ASIC Test subordinates all of its functions to and is in compliance with the IEEE Std.1149.1a-1993 above restrictions and/or recommendations.
Unfortunately, this test method has several shortcomings: (a) limited circuit visibility, (b) low test frequency, and (c) artificial circuit stimulation. J. A. Waicukauski, E. Lindbloom, B. Rosen, V. Iyengrar, "Transition Fault Simulation by Parallel Pattern Single Fault Propagation", International Test Conference 1994 Proceedings, "TEST: The Next 25 Years" pp. 253-259, International Test Conference 205 Tennyson Ave, Suite C, Altoona, Pa. 16602. Published in 1994. Isolating faults to particular ASICs becomes a major obstacle in the troubleshooting of defective Printed Board Assemblies (PBAs). Present testing techniques do not address the problems associated with testing large complex circuits containing synchronous, sequential logic. The long frames of high speed serial data required to test and control circuits of this nature are difficult to simulate or detect using present testing techniques and commercial test equipment.
For example, bytes of information can exist embedded in a design, which may be accessible only through slow, complex, and proprietary interfaces which may automatically dispense this information at regular intervals. This arrangement becomes a virtual roadblock to the present test methodology, which has little control over the acquisition of needed test information from the device. A way to circumvent this interface in order to retrieve information in a timely matter is required.
Presently, the leading role in circuit implementation is taken by the ASIC. Although the use of ASICs has been widely accepted in the electronics industry, the advancement of this technology has not focused enough on ASIC testability. One aspect of improved ASIC testability is described below.